University Event

Engineering Taster Session: Digital Logic

University event offered by Manchester Metropolitan University

Event Summary:

A-Level, BTEC and T-Level linked taster session on Digital Logic for students who are studying or are interested in computing.

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Full Event Details:

During this session operation of synchronous digital logic circuits such as ripple counters, Johnson counters and shift registers will be investigated. Simulation of digital circuits will be accomplished using Multisim Live (web based package).

This session lasts between 60-90 minutes. The main session is preceded by a welcome presentation and ends with a Q&A where students are free to ask questions. It is aimed at year group 12 and 13 and is delivered via MS Teams.

Suitable For:

Bookings by Teachers for Key Stage 5 (Students aged 16-18)

Duration:

Short Session

Dates Available:

This event is delivered online

Minimum number of students:

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